(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating very fine lines as part of the process of creating semiconductor devices.
(2) Description of the Prior Art
The continued effort to reduce device dimensions and to therewith improve device electrical performance requires high accuracy formation of conductive lines, conductive patterns and conductive connectors of sub-micron dimensions. These sub-micron conductive elements may be elements of an individual semiconductor device or may be elements that form conductive interconnects between co-functional semiconductor devices within one larger package.
A conventional process for creating sub-micron conductive lines and patterns uses a lift-off process. This process is briefly highlighted using FIGS. 1 and 2.
Shown in the cross section of FIG. 1 are the following elements:                10, the surface of a substrate, typically a monocrystalline silicon substrate        12, a layer of insulation that is created over the surface of substrate 10        14, a layer of conductive material in which the sub-micron conductive lines and patterns are to be created; the conductive material 14 can comprise metal, polysilicon, amorphous silicon or any other semiconductor compatible conductive layer        16, a layer of exposure sensitive material that is used for the creation of an etch mask over the surface of layer 14; layer 16 typically comprises photoresist, which can be developed by exposing the irradiated surface of layer 16 to a solvent that is capable of dissolving the irradiated portion (that is a positive-tone photoresist has been used) or that that is capable of dissolving the non-irradiated portion (that is a negative-tone photoresist has been used).        
The preferred technology that is applied for the creation of the openings 15 in layer 16 of exposure sensitive material is photolithography. Key parameters in this exposure are the cross section of openings 15, that is the feature width of the created sub-micron conductive lines and patterns, and the distance between openings 15, which is the separation of the created sub-micron conductive lines and patterns.
Significant improvements in the art of photolithography have enabled continued reduction of the critical dimensions of the sub-micron conductive lines and patterns. Efforts continue to be dedicated to improvements of photolithographic technology. These efforts have led to for instance the use of and improvements in phase shifting masks and alternate phase shifting masks. One of the major objectives of these improvements is to reduce proximity effects of the light beams that are used for the exposure of an exposure sensitive surface such as the surface of layer 16, shown in the cross section of FIG. 1, of photoresist. These efforts however result in a significant increase in the cost of creating semiconductor devices, which is a trend that must be avoided in the highly cost-sensitive and competitive semiconductor manufacturing industry.
Another approach that has been used to create sub-micron conductive lines and patterns is to increase the frequency of the source of energy that is used with photolithography processes. As such have been applied the use of I-line (365 nm) exposure, combined with high-resolution photoresist and the use of Deep UV (248 nm) exposure. Both of these methods however result in an increased manufacturing cost.
The sub-micron conductive lines and patterns of FIG. 1 are created by etching (lifting-off) the underlying conductive layer 14, FIG. 1, in accordance with the pattern that has been created in the exposure sensitive layer 16, after which the mask 16 can be removed from the surface of the created pattern 14, FIG. 2.
The invention provides a method that addresses the above stated concerns relating to the creation of sub-micron conductive lines and patterns by using photolithography technology. The method of the invention alleviates requirements that are typically imposed on the equipment, that is used during the process of photolithographic exposure for the creation of sub-micron conductive lines and patterns.
U.S. Pat. No. 6,100,014 (Lin et al.) shows a photo process to form a small opening using spacer on a resist layer.
U.S. Pat. No. 6,239,008 (Yu) shows a photo process to form a dense pattern by a double deposition process.
U.S. Pat. No. 4,702,792 (Chow et al.), U.S. Pat. No. 5,888,904 (Wu), U.S. Pat. No. 4,496,419 (Nulman et al.), U.S. Pat. No. 4,954,218 (Okumura et al.), U.S. Pat. No. 4,759,822 (Vetanen et al.) are related processes.